The present invention relates to semiconductor design technology, and more particularly, to a write driver of a semiconductor memory device.
Product costs are being reduced by decreasing an area occupied by internal circuits of a semiconductor memory device and thus producing a number of semiconductor memory devices with one wafer.
FIG. 1 illustrates a semiconductor memory device of the prior art.
Referring to FIG. 1, the semiconductor memory device includes a first memory bank, UPPER BANK, and a second memory bank, LOWER BANK, a plurality of first write drivers 11U, 12U, 13U and 14U for driving a multiplicity of write data DATA_IN0, DATA_IN1, DATA_IN2 and DATA_IN3 to the first memory bank, UPPER BANK, and a plurality of second write drivers 11L, 12L, 13L and 14L for driving the multiplicity of write data DATA_IN0, DATA_IN1, DATA_IN2 and DATA_IN3 to the second memory bank, LOWER BANK.
The plurality of first write drivers 11U, 12U, 13U and 14U and the plurality of second write drivers 11L, 12L, 13L and 14L are disposed in a column decoding area YDEC AREA between the first memory bank, UPPER BANK and the second memory bank, LOWER BANK. In the mean time, the first memory bank, UPPER BANK and the second memory bank, LOWER BANK are selectively activated by a bank selection signal and the write drivers corresponding to the activated memory bank drive the multiplicity of write data DATA_IN0, DATA_IN1, DATA_IN2 and DATA_IN3 to the activated memory bank.
The plurality of first write drivers 11U, 12U, 13U and 14U transfer the multiplicity of write data DATA_IN0, DATA_IN1, DATA_IN2 and DATA_IN3 to memory cells within the first memory bank, UPPER BANK through transmission lines U1, U2, U3 and U4 of the first memory bank, UPPER BANK. Meanwhile, the plurality of second write drivers 11L, 12L, 13L and 14L transfer the multiplicity of write data DATA_IN0, DATA_IN1, DATA_IN2 and DATA_IN3 to memory cells within the second memory bank, LOWER BANK through transmission lines D1, D2, D3 and D4 of the second memory bank, LOWER BANK. For reference, the transmission lines U1, U2, U3 and U4 of the first memory bank, UPPER BANK and the transmission lines D1, D2, D3 and D4 of the second memory bank, LOWER BANK have the same column location information.
As described above, the semiconductor memory device of the prior art includes write drivers whose number is the same as that of transmission lines of each memory bank and thus an area occupied by the write drivers is very great.
FIG. 2 illustrates a write driver of the prior art.
Referring to FIG. 2, the write driver includes a write control block 21 for generating drive control signals LAT, LATB, DRV and DRVB corresponding to write data DIN and DINB, and a write drive block 22 for driving transmission lines LIO and LIOB of a memory bank in response to the drive control signals LAT, LATB, DRV and DRVB.
The detailed construction and major operations of the write driver will be described hereinafter.
The write control block 21 includes an enable signal generating sector 210 for generating a drive enable signal BWENP in response to a write signal BWEN and a write mask signal WDM, and a drive control signal generating sector 220 for generating the drive control signals LAT, LATB, DRV and DRVB corresponding to the write data DIN and DINB in response to the drive enable signal BWENP.
Herein, the enable signal generating sector 210 includes a first inverter INV1 to receive the write signal BWEN, a second inverter INV2 to receive the write mask signal WDM, a switching unit TG for selectively outputting an output signal of the second inverter INV2 in response to the write signal BWEN, a latching unit 211 for storing an output signal of the switching unit TG and a logical combining unit NOR1 for generating the drive enable signal BWENP by performing a NOR operation on output signals of the first inverter INV1 and the latching unit 211.
When the write signal BWEN has a low level, the switching unit TG is turned on and thus the latching unit 211 stores the write mask signal WDM to determine whether to perform a mask operation. If the write signal BWEN is enabled to a high level and the write mask signal WDM has a low level, the drive enable signal BWENP generated from the logical combining unit NOR1 is enabled to a high level, thereby activating the drive control signal generating sector 220.
Furthermore, the drive control signal generating sector 220 includes a cross couple latch amplifier 221 for receiving the write data DIN and DINB of a differential type and outputting the drive control signals LAT, LATB, DRV and DRVB through its differential output nodes N1 and N2. The drive control signal generating sector 220 further includes a precharging unit 222 for precharging the differential output nodes N1 and N2 in response to the drive enable signal BWENP. That is, the cross couple latch amplifier 221 includes loading elements MP1, MP2, MN1 and MN2 connected between a supply voltage (VDD) terminal and differential input elements MN3 and MN4 and controlled by voltage levels of the differential output nodes N1 and N2, a first inverter, INV1, and a second inverter, INV2, to receive the drive control signals LAT and LATB outputted through the differential output nodes N1 and N2, respectively, the differential input elements MN3 and MN4 to receive the write data DIN and DINB of a differential type, and a bias element MN5 for providing a bias current to the differential input elements MN3 and MN4 in response to the drive enable signal BWENP. In addition, the precharging unit 222 includes a plurality of PMOS transistors MP11, MP12 and MP13 for providing a precharge voltage VDD to the differential output nodes N1 and N2 under the control of the drive enable signal BWENP.
First of all, if the drive enable signal BWENP has a low level, the bias element MN5 does not provide the bias current to the differential input elements MN3 and MN4 and thus the cross couple latch amplifier 221 is not activated. As a result, the PMOS transistors MP11, MP12 and MP13 of the precharging unit 222 are turned on in response to the drive enable signal BWENP so that the differential output nodes N1 and N2 are precharged with the precharge voltage VDD.
Then, if the drive enable signal BWENP becomes to have a high level, the precharge operation on the differential output nodes N1 and N2 of the precharging unit 222 is terminated and the cross couple latch amplifier 221 outputs the drive control signals LAT, LATB, DRV and DRVB corresponding to the write data DIN and DINB inputted thereto.
The write drive block 22 includes differential driving sectors 230 and 240 for differentially driving a positive and a negative transmission line LIO and LIOB of the memory bank in response to the drive control signals LAT, LATB, DRV and DRVB, and a transmission line precharging sector 250 for precharging the positive transmission line, LIO and the negative transmission line, LIOB of the memory bank in response to a precharge signal LIOPCG.
The write drive block 22 precharges the positive transmission line LIO and the negative transmission line LIOB with a precharge voltage VPRE if the precharge signal LIOPCG has a high level. Then, if the precharge signal LIOPCG has a low level and the drive control signals LAT, LATB, DRV and DRVB are enabled, the positive transmission line LIO and the negative transmission line LIOB are differentially driven according to the drive control signals LAT, LATB, DRV and DRVB.
As described above, since the prior art should include write drivers whose number is identical to the number of transmission lines of each memory bank, the write drivers occupy a large area. Therefore, technology for resolving the above problem is required.